Several types of semi-volatile or non-volatile programmable resistance memory cells have been developed. Magnetic random access memory (“MRAM”) is one such type of programmable resistance memory device, which utilizes magnetic vector orientations to store data. MRAM devices do not have to be periodically refreshed and could be used for long-term data storage. In addition, read and write operations performed on MRAM devices are orders of magnitude faster than read and write operations performed on conventional long-term storage devices such as hard drives and non-volatile memory, such as Flash or electrically erasable programmable read-only memory devices. Furthermore, MRAM devices are potentially more compact because the memory cells are stackable. Thus, MRAM devices have a potential to be ideal memory devices because they are randomly accessible, offer very quick read and write times, are non-volatile, but highly alterable, and do not need to be refreshed as compare with conventional DRAM memory devices.
A typical MRAM device includes an array of memory cells. Word lines extend along rows of the array, and bit lines extend along columns of the array. Each memory cell is located at a cross point of a word line and a bit line. Each memory cell stores a bit of information as an orientation of magnetization vectors of a pinned and free ferromagnetic layer. The free and pinned magnetization vectors of each memory cell assume one of two stable orientations at any given time. These two stable orientations, often referred to as parallel and anti-parallel, represent logic “1” or “0” states respectively.
The magnetization vector orientation affects the resistance of the MRAM memory cell. As a result, the relative magnetization vector orientation of a selected memory cell and, therefore, the logic state of the memory cell may be read by sensing the resistance of the cell. For example, when the relative orientation of the vector magnetization is parallel, the cell's resistance is low and the value of the memory cell has a logic 1 state. However if the relative orientation of the magnetization vector is anti-parallel, the cell exists in a high resistance state representing a logic 0 state.
The logic state of a selected MRAM memory cell may be sensed by applying a voltage to the cell, measuring a sense current that flows through the cell and determining its resistance state through a direct reading. Ideally, the resistance would be proportional to the sense current. The logic state of the selected memory cell may also be sensed by applying a voltage to the cell. However, instead of measuring the sense current flowing through the cell, the current is converted to a voltage by integrating the sense current over a period of time. The voltage is then measured in order to determine the resistance of the memory cell.
Sensing the logic state of an MRAM memory cell using current or voltage sensing techniques is challenging due to the configuration of the MRAM cross matrix array structure, which imposes multiple design constraints on the device. In particular, the need for high storage density and low cost warrants the minimizing of the number of transistors in the memory array. As such, a cell in a cross point array does not include an access transistor. As a result, each resistive element remains operatively connected to respective row and column lines at all times. Consequently, as a memory cell is sensed, it is shunted by a significant leakage current path. In a conventional MRAM device, an element in a high resistance state may have a resistance of about 1MΩ, while an element in a low resistance state may have a resistance of about 950 KΩ. The differential resistance between a logic one and a logic zero is about 50 KΩ or 5% of scale. Rapidly distinguishing a 5% resistance differential on a scale of 1MΩ in the face of low resistance leakage paths through neighboring cells and with a minimum of circuitry is a challenge.
In the current and voltage sensing schemes described above, a direct measurement of resistance is involved. A read-write-read-write_restore technique is employed which uses the direct resistance reading to determine the logic state of the MRAM cell. This technique determines the logic state of a cell by reading the resistance of a cross matrix memory cell by either current or voltage integration. A known value is subsequently written to the cell, for example, a logic 1. The cell is read a second time to determine if the resistance state of the has changed with regard to the previous read. If there is no change between the two reads cycles, the resistance state of the cell is equivalent to the known value, and the cell is left unaltered. If there is a change in the resistance of the cell between read cycles, the cell value is not equal to the known value, and the original resistance value is written back to the cell in order to restore the cell to its original state.
However, this technique may not result in an accurate determination of the logic state of the MRAM cell because of the close resistance value between the logic 0 and logic 1 resistance states and cell to cell processing variations. Consequently, this technique requires additional operations to determine the logic state of an MRAM cell. Accordingly, there is a need and desire for another method of sensing the logic state of a programmable resistance memory cell, for example, an MRAM cell.